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Our implementation plan should then target an innovative vision for the development of such target generic SOI platform enabling short- and long-term achievements. Our vision builds on the recent manufacture of multi-layered SOI wafers by SOITEC using the Smart-Cut technique in which:
• thin SOI layers (i.e. 100 nm) could be integrated with thick SOI layers (few microns) to allow the 3D co-integration and in-situ interconnection and wafer-level packaging of, on one hand ULP or high-temperature SOI CMOS electronics or thin-film sensor, with on the other hand MEMS pressure or acceleration sensors fabricated in the more adequate thick silicon (e.g. 20 µm).
• or similarly, SiC membranes could be integrated along with SOI CMOS circuits for sensor resistance to even harsher environments.
A consortium to carry out the related R&D project could be built out of the following possible partner organisations list, joining the most relevant expertises, in industries and universities, towards sensors/circuits co-integration in relation with applications: Multi-SOI wafer provider (SOITEC, CEA-LETI); Thick film SOI MEMS design and production (Tronic’s, Kulite, Thales, EADS, CEA-LETI, Auxitrol); Thin film SOI MEMS/sensors design and fabrication (UCL, X-FAB, IMS, DALSA, Honeywell, ITE); Thin film SOI IC design house (CISSOID); Thin film SOI IC fabrication (UCL, X-FAB, DALSA, Honeywell, ITE); Gas SOI and SiC sensors (UCL, EADS, TUB, Sochinor); End-users (EADS (Airbus), Snecma (TechSpaceAero), Lockheed, Boeing, NASA, ESA); Packaging / System Houses (TRW, Kistler); Multi-physics/dimensions simulations of mechanical structures (CENAERO).
From that list, three potential industrial platforms appear: the first is European (X-FAB), the second is US (Honeywell) and the third one is Canadian (DALSA). Depending on the ambitions and exact objectives, a pilot project from a few millions euros up to 10 millions could join a number of these participants in a three-year timeframe with three successive phases:
- Year 1: Compatibilization of now separated MEMS, sensors and circuits developments (i.e. establish MEMS/sensor co-fabrication process flow).
- Year 2: First non-optimized partial realization (design, fabrication, test)
- Year 3: Optimized demonstrator trial (2nd design, fabrication and test).
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