3. Baseline Use

The baseline use of SOI technology must be examined in a very broad scope. One of the main challenges in microsystems development and deployment lies in the full system miniaturization, from energy sources to communication antennas, which today is in particular limited by board level assembly of multiple components. New research directions therefore evolve from pure MOS transistor scaling (i.e. Moore’s law) to the incorporation of new functions (sensors, MEMS, energy scavenging…) on the silicon chips themselves, in addition to the MOS circuitry. It is then extremely important to note that SOI appears as a major and mature contender in both directions. With regards to CMOS scaling to the nanoscale, the well-known ITRS roadmap indeed points out SOI as one of the solution to sustain Moore’s law in the next future.

With regards to the co-integration of new functionalities above high-quality CMOS ICs, at wafer level, SOI technology has also demonstrated unique compatibility and performance properties. The SOI substrates indeed intrinsically allow to combine all its well-known circuit advantages, of huge interest for the targeted applications (i.e. micropower consumption, harsh environment resistance, RF operation…), with high-performance sensors and MEMS free of the parasitics due to the bulk Si substrate or to off-chip connections, as well be detailed here below.